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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com ? ? ? ? st16c1450/51 2.97v to 5.5v uart october 2003 rev. 4.2.0 general description the st16c1450, st16c1451 series (here on denoted as the 145x) is a universal asynchronous receiver and transmitter (uart). the 145x is foot print compatible to the ssi 73m1550 and ssi 73m2550 uart with one byte fifo and higher operating speed and lower access time. the 145x provides enhanced uart functions with a modem control interface, independent programmable baud rate generators with clock rates to 1.5 mbps. onboard status registers provide the user with error indications and operational status. system interrupts and modem control features may be tailored by external software to meet specific user requirements. an internal loop- back capability allows onboard diagnostics. the 145x is available in a 28-pin plcc/plastic-dip, 48-pin tqfp packages. the baud rate generator can be configured for either crystal or external clock input with the exception of the 28 pin 1451 package. an external clock must be provided for the 28 pin 1451 package. each package type, with the exception of the 28 pin 1450, provides a buffered reset output that can be controlled through user software. the 145x is fabricated in an advanced cmos process to achieve low drain power and high speed requirements. the st16c145x is not compatible with the industry standard 16450 and will not work with the standard serial port driver in ms windows (see pages 15-16 for details) . for a ms windows compatible uart, see the st16c450. features pin and functionally compatible to ssi 73m1550/ 2550 1 byte transmit fifo (thr) 1 byte receive fifo with error tags (rhr) four levels of prioritized interrupts modem control signals (cts#, rts#, dsr#, dtr#, ri#, cd#) programmable character lengths (5, 6, 7, 8) with even, odd or no parity crystal or external clock input (except 28 pin st16c1451, external clock only) 1.5 mbps transmit/receive operation (24 mhz) with programmable clock control power down mode (50 ua at 3.3 v, 200 ua at 5 v) software controllable reset output 2.97 to 5.5 volt operation applications battery operated electronics internet appliances handheld terminal personal digital assistants cellular phones dataport f igure 1. b lock d iagram xtal1/clk xtal2 crystal osc/buffer dtr#, rts# dsr#, cts#, cd#, ri# data bus interface thr baud rate generator transmitter uart configuration regs ior# rhr receiver modem control signals tx rx int a2:a0 d7:d0 cs# iow # reset rst
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 2 f igure 2. st16c1450 p inouts 28-plcc packages 48-tqfp package 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 n.c. n.c. d4 d5 d6 d7 rx tx cs# n.c. n.c. n.c. n.c. n.c. cts# reset dtr# rts# a0 n.c. a1 a2 n.c. n.c. n.c. d3 d2 d1 n.c. d0 n.c. vcc cd# dsr# n.c. n.c. n.c. n.c. xtal1 xtal2 iow# n.c. gnd ior# ri# rst int n.c. st16c1450cq48 4 3 2 1 28 27 26 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 17 18 d4 d5 d6 d7 rx tx cs# cts# reset dtr# rts# a0 a1 a2 d3 d2 d1 d0 vcc cd# dsr# xtal1 xtal2 iow# gnd ior# ri# int st16c1450cj28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d0 d1 d2 d3 d4 d5 d6 d7 rx tx cs# xtal1 xtal2 iow# vcc cd# dsr# cts# reset dtr# rts# a0 a1 a2 int ri# ior# gnd st16c1450cp28 28-pdip packages n ote : pinouts not to scale . actual size of tqfp package is smaller than plcc package .
? ? ? ? st16c1450/51 rev. 4.2.0 2.97v to 5.5v uart 3 f igure 3. st16c1451 p inouts 28-plcc packages 48-tqfp package 4 3 2 1 28 27 26 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 17 18 d4 d5 d6 d7 rx tx cs# cts# reset dtr# rts# a0 a1 a2 d3 d2 d1 d0 vcc cd# dsr# clk iow# gnd ior# ri# rst int st16c1451cj28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d0 d1 d2 d3 d4 d5 d6 d7 rx tx cs# clk iow# gnd vcc cd# dsr# cts# reset dtr# rts# a0 a1 a2 int rst ri# ior# ST16C1451CP28 28-pdip packages n ote : pinouts not to scale . actual size of tqfp package is smaller than plcc package . 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 n.c. n.c. d4 d5 d6 d7 rx tx cs# n.c. n.c. n.c. n.c. n.c. cts# reset dtr# rts# a0 n.c. a1 a2 n.c. n.c. n.c. d3 d2 d1 n.c. d0 n.c. vcc cd# dsr# n.c. n.c. n.c. n.c. xtal1 xtal2 iow# n.c. gnd ior# ri# rst int n.c. st16c1451cq48
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 4 ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus st16c1450cp28 28-lead pdip 0c to +70c discontinued. see the st16c1450cq48 for a replacement. st16c1450cj28 28-lead plcc 0c to +70c active st16c1450cq48 48-lead tqfp 0c to +70c active ST16C1451CP28 28-lead pdip 0c to +70c discontinued. see the st16c1450cq48 for a replacement. st16c1451cj28 28-lead plcc 0c to +70c discontinued. see the st16c1450cq48 for a replacement. st16c1451cq48 48-lead tqfp 0c to +70c discontinued. see the st16c1450cq48 for a replacement. st16c1450ip28 28-lead pdip -40c to +85c discontinued. see the st16c1450iq48 for a replacement. st16c1450ij28 28-lead plcc -40c to +85c active st16c1450iq48 48-lead tqfp -40c to +85c active st16c1451ip28 28-lead pdip -40c to +85c discontinued. see the st16c1450iq48 for a replacement. st16c1451ij28 28-lead plcc -40c to +85c discontinued. see the st16c1450iq48 for a replacement. st16c1451iq48 48-lead tqfp -40c to +85c discontinued. see the st16c1450iq48 for a replacement.
? ? ? ? st16c1450/51 rev. 4.2.0 2.97v to 5.5v uart 5 pin descriptions n ame 28-p in pdip (1450) 28-p in pdip (1451) 28-p in plcc (1450) 28-p in plcc (1451) 48-p in tqfp (145x) t ype d escription data bus interface a0 a1 a2 21 20 19 21 20 19 21 20 19 21 20 19 30 28 27 i address data lines [2:0]. a2:a0 selects internal uarts configuration registers. d0 d1 d2 d3 d4 d5 d6 d7 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 43 45 46 47 3 4 5 6 i/o data bus lines [7:0] (bidirectional). ior# 16 15 16 15 20 i input/output read (active low). the falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [a2:a0], places it on the data bus to allow the host processor to read it on the leading edge. iow# 14 13 14 13 17 i input/output write (active low). the falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines [a2:a0]. cs# 11 11 11 11 9 i chip select input (active low). a logic 0 on this pin selects the st16c145x device. int 18 18 18 18 23 o interrupt output (three-state, active high). int output defaults to three-state mode and becomes active high when mcr bit-3 is set to a logic 1. int output becomes a logic high level when interrupts are enabled in the interrupt enable register (ier), and whenever the transmitter, receiver, line and/or modem status register has an active condition. modem or serial i/o interface tx 10 10 10 10 8 o transmit data. this output is associated with individual serial transmit channel data from the 145x. the tx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. during the local loopback mode, the tx output pin is disabled and tx data is internally con- nected to the uart rx input. rx 9 9 9 9 7 i receive data. this input is associated with individual serial channel data to the 145x. normal received data input idles at logic 1 condition. this input must be connected to its idle logic state, logic 1, else the receiver may report receive break and/or error condition(s).
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 6 rts# 22 22 22 22 31 o request to send or general purpose output (active low). if this pin is not needed for modem communication, then it can be used as a general i/o. if it is not used, leave it uncon- nected. cts# 25 25 25 25 34 i clear to send or general purpose input (active low). if this pin is not needed for modem communication, then it can be used as a general i/o. if it is not used, connect it to vcc. dtr# 23 23 23 23 32 o data terminal ready or general purpose output (active low). if this pin is not needed for modem communication, then it can be used as a general i/o. if it is not used, leave it unconnected. dsr# 26 26 26 26 39 i data set ready input or general purpose input (active low). if this pin is not needed for modem communication, then it can be used as a general i/o. if it is not used, connect it to vcc. cd# 27 27 27 27 40 i carrier detect input or general purpose input (active low). if this pin is not needed for modem communication, then it can be used as a general i/o. if it is not used, connect it to vcc. ri# 17 16 17 16 21 i ring indicator input or general purpose input (active low). if this pin is not needed for modem communication, then it can be used as a general i/o. if it is not used, connect it to vcc. ancillary signals clk - 12 - 12 - i external clock input. this function is associated with 28 pin pdip and 28 pin plcc st16c1451 packages only. an external clock must be connected to this pin to clock the baud rate generator and internal circuitry. xtal1 12 - 12 - 15 i crystal or external clock input. see figure 4 for typical oscillator connections. xtal2 13 - 13 - 16 o crystal or buffered clock output. see figure 4 for typical oscillator connections. reset 24 24 24 24 33 i reset input (active high). when it is asserted, the uart configuration registers are reset to default values, see ta b l e 6 . rst - 17 - 17 22 o reset output (active high). this output is only available on the st16c1451. when ier bit-5 is a logic 0, rst will follow the logical state of the reset pin. when ier bit-5 is a logic 1, the user may send software (soft) resets via mcr bit-2. soft resets from mcr bit-2 are ored with the state of the reset pin. vcc 28 28 28 28 41 pwr power supply input of 2.97 to 5.5v. n ame 28-p in pdip (1450) 28-p in pdip (1451) 28-p in plcc (1450) 28-p in plcc (1451) 48-p in tqfp (145x) t ype d escription
? ? ? ? st16c1450/51 rev. 4.2.0 2.97v to 5.5v uart 7 pin type: i=input, o=output, i/o= input/output, od=output open drain. 1.0 product description the st16c145x provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to- parallel data conversions for both the transmitter and receiver sections. these functions are necessary for converting the serial data stream into parallel data that is required in digital data systems. synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). data integrity is ensured by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the 145x is capable of operation up to 1.5 mbps with a 24 mhz crystal or external clock input with a 16x sampling clock (at vcc = 5.0v). with a crystal of 14.7456 mhz and through a software option, the user can select data rates up to 921.6 kbps. 2.0 functional descriptions 2.1 internal registers the 145x has a set of enhanced registers for controlling, monitoring and data loading and unloading. these registers function as data holding registers (thr/rhr), interrupt status and control registers (isr/ier), a fifo control register (fcr), receive line status and control registers (lsr/lcr), modem status and control registers (msr/mcr), programmable data rate (clock) divisor registers (dll/dlm), and a user accessible scractchpad register (spr). all the register functions are discussed in full detail later in section 3.0, uart internal registers on page 13 . gnd 15 14 15 14 19 pwr power supply common ground. n.c.----1, 2, 10-14, 18, 24-26, 29, 35-38, 42, 44, 48 - not connected. n ame 28-p in pdip (1450) 28-p in pdip (1451) 28-p in plcc (1450) 28-p in plcc (1451) 48-p in tqfp (145x) t ype d escription
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 8 2.2 crystal oscillator or external clock the 145x includes an on-chip oscillator (xtal1 and xtal2). the crystal oscillator provides the system clock to the baud rate generators (brg) in the uart. xtal1 is the input to the oscillator or external clock buffer input with xtal2 pin being the output. for programming details, see section 2.3, programmable baud rate generator on page 8 . the on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100ppm frequency tolerance) connected externally between the xtal1 and xtal2 pins (see figure 4 ). alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates. typical oscillator connections are shown in figure 4 . for further reading on oscillator circuit please see application note dan108 on exars web site. 2.3 programmable baud rate generator the uart has its own baud rate generator (brg). the brg divides the input crystal or external clock by a programmable divisor between 1 and (2 16 -1) to obtain a 16x sampling clock of the serial data rate. the sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor (dll and dlm registers) defaults to a random value upon power up or a reset. therefore, the brg must be programmed during initialization to the operating data rate. programming the baud rate generator registers dlm and dll provides the capability of selecting the operating data rate. ta b l e 1 shows the standard data rates available with a 14.7456 mhz crystal or external clock at 16x clock rate. when using a non-standard data rate crystal or external clock, the divisor value can be calculated for dll/dlm with the following equation. f igure 4. t ypical oscillator connections divisor (decimal) = (xtal1 clock frequency) / (serial data rate x 16) c1 22-47pf c2 22-47pf y1 1.8432 mhz to 24 mhz r1 0-120 (optional) r2 500k - 1m xtal1 xtal2
? ? ? ? st16c1450/51 rev. 4.2.0 2.97v to 5.5v uart 9 2.4 transmitter the transmitter section comprises of an 8-bit transmit shift register (tsr) and 16 bytes of fifo which includes a byte-wide transmit holding register (thr). tsr shifts out every data bit with the 16x internal clock. a bit time is 16 clock periods. the transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). the status of the fifo and tsr are reported in the line status register (lsr bit-5 and bit-6). 2.4.1 transmit holding register (thr) - write only the transmit holding register is an 8-bit register providing a data interface to the host processor. the host writes transmit data byte to the thr to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-significant-bit (bit-0) becomes first data bit to go out. the thr is the input register to the transmit fifo of 16 bytes when fifo operation is enabled by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. 2.4.2 transmitter operation the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a transmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr becomes completely empty. t able 1: t ypical data rates with a 14.7456 mh z crystal or external clock o utput data rate d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) d ata r ate e rror (%) 400 2304 900 09 00 0 2400 384 180 01 80 0 4800 192 c0 00 c0 0 9600 96 60 00 60 0 19.2k 48 30 00 30 0 38.4k 24 18 00 18 0 76.8k 12 0c 00 0c 0 153.6k 6 06 00 06 0 230.4k 4 04 00 04 0 460.8k 2 02 00 02 0 921.6k 1 01 00 01 0
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 10 2.5 receiver the receiver section contains an 8-bit receive shift register (rsr) and a byte-wide receive holding register (rhr). the rsr uses the 16x clock for timing. it verifies and validates every bit on the incoming character in the middle of each data bit. on the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16x clock rate. after 8 clocks the start bit period should be at the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if there were any error(s), they are reported in the lsr register bits 2-4. upon unloading the receive data byte from rhr, the error tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiving a characterthe rhr interrupt is enabled by ier bit-0. 2.5.1 receive holding register (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. when there is data in the rhr register, the 3 error tags in lsr register (bits 2-4) indicates if there are any errors associated with that byte. f igure 5. t ransmitter o peration transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x clock
? ? ? ? st16c1450/51 rev. 4.2.0 2.97v to 5.5v uart 11 2.6 special (enhanced feature) mode the 145x supports the standard features of the st16c450. in addition the 145x supports some enhanced features not available for the st16c450. these features are enabled by ier bit-5 and include a software controllable (soft) reset, power down feature and fifo monitoring bits. 2.6.1 soft reset soft resets are useful when the user desires the capability of resetting an externally connected device only. mcr bit-2 can be used to initiate a soft reset at the rst output pin. this does not reset the 145x (only the reset input pin can reset the 145x). soft resets from mcr bit-2 are ored with the reset input pin. therefore both reset types will be seen at the rst output pin. 2.6.2 power down mode the power down feature (controlled by mcr bit-7) provides the user with the capability to conserve power when the package is not in actual use without destroying internal register configuration data. this allows quick turnarounds from power down to normal operation. 2.7 internal loopback the 145x uart provides an internal loopback capability for system diagnostic purposes. the internal loopback mode is enabled by setting mcr register bit-4 to logic 1. all regular uart functions operate normally. figure 7 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. the tx pin is held at logic 1 or mark condition while rts# and dtr# are de-asserted, and cts#, dsr# cd# and ri# inputs are ignored. caution: the rx input must be held to a logic 1 during loopback test else upon exiting the loopback test the uart may detect and report a false break signal. f igure 6. r eceiver o peration in non -fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x clock receive data characters data bit validation error tags in lsr bits 4:2
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 12 f igure 7. i nternal l oopback tx rx modem / general purpose control logic internal data bus lines and control signals rts# mcr bit-4=1 vcc vcc transmit shift register receive shift register cts# dtr# dsr# ri# cd# op1# op2# rts# cts# dtr# dsr# ri# cd# vcc
? ? ? ? st16c1450/51 rev. 4.2.0 2.97v to 5.5v uart 13 3.0 uart internal registers the 145x has a set of configuration registers selected by address lines a0, a1 and a2. the 16c450 compatible registers can be accessed when lcr[7] = 0 and the baud rate generator divisor registers can be accessed when lcr[7] = 1. the complete register set is shown on ta b l e 2 and ta b l e 3 . t able 2: st16c145x uart internal registers a2,a1,a0 a ddresses r egister r ead /w rite c omments 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - div latch low byte read/write lcr[7] = 1 0 0 1 dlm - div latch high byte read/write 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 1 0 isr - interrupt status register reserved read-only write-only 0 1 1 lcr - line control register read/write 1 0 0 mcr - modem control register read/write lcr[7] = 0 1 0 1 lsr - line status register reserved read-only write-only 1 1 0 msr - modem status register reserved read-only write-only 1 1 1 spr - scratch pad register read/write
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 14 . t able 3: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier rd/wr 0 0 special mode enable (enable mcr bits 7, 2) 0 modem status int. enable rx line status int. enable tx empty int. enable rx data int. enable 0 1 0 isr rd 0 0 0 0 int source bit-3 int source bit-2 int source bit-1 int source bit-0 0 1 1 lcr rd/wr divisor enable set tx break set parity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 mcr rd/wr 0/ 0 0 internal loop- back enable (op2#)/ int output enable (op1#)/ rts# output control dtr# output control lcr[7] = 0 power down mode soft reset 1 0 1 lsr rd 0 thr & tsr empty thr empty rx break rx framing error rx parity error rx over- run error rx data ready 1 1 0 msr rd cd# input ri# input dsr# input cts# input delta cd# delta ri# delta dsr# delta cts# 1 1 1 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 baud rate generator divisor 0 0 0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 1 0 0 1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
? ? ? ? st16c1450/51 rev. 4.2.0 2.97v to 5.5v uart 15 4.0 internal register descriptions 4.1 receive holding register (rhr) - read- only see receiver on page 10. 4.2 transmit holding register (thr) - write-only see transmitter on page 9. 4.3 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are reported in the interrupt status register (isr). ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data character. logic 0 = disable the receive data ready interrupt (default). logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready interrupt which is issued whenever the thr is empty. if the thr is empty when this bit is enabled, an interrupt will be generated. note that this interrupt does not behave in the same manner as the industry standard 16c550. see interrupt clearing: on page 16. logic 0 = disable transmit ready interrupt (default). logic 1 = enable transmit ready interrupt. ier[2]: receive line status interrupt enable if any of the lsr register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in the rhr. logic 0 = disable the receiver line status interrupt (default). logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable logic 0 = disable the modem status register interrupt (default). logic 1 = enable the modem status register interrupt. ier[4]: reserved ier[5]: special mode enable logic 0 = disable special mode functions (default). logic 1 = enable special mode functions in addition to basic st16c1450 functions. enables isr bits 4-5 (txrdy/rxrdy), mcr bit-2 (soft reset) and mcr bit-7 (power down) functions. ier[7:6]: reserved 4.4 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current highest pending interrupt level to be serviced, others are queued up to be serviced next. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, ta b l e 4 , shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels.
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 16 4.4.1 interrupt generation: lsr is by any of the lsr bits 1, 2, 3 and 4. rxrdy is by received data in rhr. txrdy is by thr empty. msr is by any of the msr bits 0, 1, 2 and 3. 4.4.2 interrupt clearing: lsr interrupt is cleared by a read to the lsr register (but flags and tags not cleared until character(s) that generated the interrupt(s) has been emptied or cleared from rhr). rxrdy interrupt is cleared by reading rhr. txrdy interrupt is cleared by a read to the isr register and disabling the txrdy interrupt (set ier bit-1 = 0), or by loading data into the tx fifo. msr interrupt is cleared by a read to the msr register. ] isr[0]: interrupt status logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. logic 1 = no interrupt pending (default condition). isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority levels (see interrupt source ta b l e 4 ). isr[7:4]: reserved 4.5 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. t able 4: i nterrupt s ource and p riority l evel p riority l evel isr r egister s tatus b its s ource of interrupt b it -3 b it -2 b it -1 b it -0 1 0 1 1 0 lsr (receiver line status register) 2 0 1 0 0 rxrdy (received data ready) 3 0 0 1 0 txrdy (transmit ready) 4 0 0 0 0 msr (modem status register) - 0 0 0 1 none (default)
? ? ? ? st16c1450/51 rev. 4.2.0 2.97v to 5.5v uart 17 lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bit in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the parity bit is a simple way used in communications for data integrity check. see ta b l e 5 for parity selection summary below. logic 0 = no parity. logic 1 = a parity bit is generated during the transmission while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logic 1, lcr bit-4 selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1s in the transmitted character. the receiver must be programmed to check the same format (default). logic 1 = even parity is generated by forcing an even number of logic 1s in the transmitted character. the receiver must be programmed to check the same format. bit-1 bit-0 w ord length 0 0 5 (default) 01 6 10 7 11 8 bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 15 1-1/2 1 6,7,8 2
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 18 lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit-5 selects the forced parity format. lcr[5] = logic 0, parity is not forced (default). lcr[5] = logic 1 and lcr[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. lcr[5] = logic 1 and lcr[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr[6]: transmit break enable when enabled, the break control bit causes a break condition to be transmitted (the tx output is forced to a space, logic 0, state). this condition remains, until disabled by setting lcr bit-6 to a logic 0. logic 0 = no tx break condition (default). logic 1 = forces the transmitter output (tx) to a space, logic 0, for alerting the remote receiver of a line break condition. lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm) enable. logic 0 = data registers are selected (default). logic 1 = divisor latch registers are selected. 4.6 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for controlling the serial/modem interface signals or general purpose inputs/outputs. mcr[0]: dtr# output the dtr# pin is a modem control output. if the modem interface is not used, this output may be used as a general purpose output. logic 0 = force dtr# output to a logic 1 (default). logic 1 = force dtr# output to a logic 0. mcr[1]: rts# output the rts# pin is a modem control output. if the modem interface is not used, this output may be used as a general purpose output. logic 0 = force rts# output to a logic 1 (default). logic 1 = force rts# output to a logic 0. t able 5: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 01 1 even parity 1 0 1 force parity to mark, 1 1 1 1 forced parity to space, 0
? ? ? ? st16c1450/51 rev. 4.2.0 2.97v to 5.5v uart 19 mcr[2]: op1# output/soft reset op1# is not available as an output pin on the 145x. but it is available for use during internal loopback mode. in the loopback mode, this bit is used to write the state of the modem ri# interface signal. logic 0 = op1# output (ri# input) is at logic 1 (default). logic 1 = op1# output (ri# input) is at logic 0. in normal operation, this bit is associated with the rst (buffered reset) output pin. the logical state of the rst pin will follow exactly the logical state of the reset pin. when ier bit-5 = 1, soft resets from mcr bit-2 are ored with the state of the reset input pin. therefore both reset types will be seen at the rst pin. note that asserting mcr bit-2 does not reset the 145x. logic 0 = the rst output pin is a logic 0 (default). logic 1 = the rst output pin is a logic 1. mcr[3]: op2# or int output enable when not in internal loopback mode: logic 0 = int output is three-state (default). logic 1 = int output is active high. op2# is not available as an output pin on the 145x. but it is available for use during internal loopback mode. in the loopback mode, this bit is used to write the state of the modem cd# interface signal. logic 0 = op2# output (cd# input) is a logic 1 (default). logic 1 = op2# output (cd# input) is a logic 0. mcr[4]: internal loopback enable logic 0 = disable loopback mode (default). logic 1 = enable local loopback mode, see loopback section and figure 7 . mcr[6:5]: reserved mcr[7]: power down enable this bit can only be accessed when ier bit-5 = 1. logic 0 = normal mode (default). logic 1 = power down mode. see power down mode on page 11. 4.7 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. if ier bit-2 is set to a logic 1, an lsr interrupt will be generated when the character that is in the rhr has an error (parity, framing, overrun, break). lsr[0]: receive data ready indicator logic 0 = no data in receive holding register (default). logic 1 = data has been received and is saved in the receive holding register. lsr[1]: receiver overrun error flag logic 0 = no overrun error (default). logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while there is data in the rhr. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the rhr, therefore the data in the rhr is not corrupted by the error.
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 20 lsr[2]: receive data parity error tag logic 0 = no parity error (default). logic 1 = parity error. the received character in rhr does not have correct parity information and is suspect. this error is associated with the character available for reading in rhr. lsr[3]: receive data framing error tag logic 0 = no framing error (default). logic 1 = framing error. the received character did not have a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[4]: receive break error tag logic 0 = no break condition (default). logic 1 = the receiver received a break signal (rx was a logic 0 for at least one character frame time). lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indicator. the thr bit is set to a logic 1 when the data byte is transferred from the transmit holding register to the transmit shift register. the bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. lsr[6]: thr and tsr empty flag this bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. lsr[7]: reserved 4.8 modem status register (msr) - read only this register provides the current state of the modem interface input signals. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used for general purpose inputs when they are not used with modem signals. msr[0]: delta cts# input flag logic 0 = no change on cts# input (default). logic 1 = the cts# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[1]: delta dsr# input flag logic 0 = no change on dsr# input (default). logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[2]: delta ri# input flag logic 0 = no change on ri# input (default). logic 1 = the ri# input has changed from a logic 0 to a logic 1, ending of the ringing signal. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[3]: delta cd# input flag logic 0 = no change on cd# input (default). logic 1 = indicates that the cd# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[4]: cts input status
? ? ? ? st16c1450/51 rev. 4.2.0 2.97v to 5.5v uart 21 cts# (active high, logical 1). normally this bit is the compliment of the cts# input. in the loopback mode, this bit is equivalent to bit-1 in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status dsr# (active high, logical 1). normally this bit is the compliment of the dsr# input. in the loopback mode, this bit is equivalent to bit-0 in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status ri# (active high, logical 1). normally this bit is the compliment of the ri# input. in the loopback mode this bit is equivalent to bit-2 in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used. msr[7]: cd input status cd# (active high, logical 1). normally this bit is the compliment of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. 4.9 scratch pad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. the content of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. t able 6: uart reset conditions registers reset state dll bits 7-0 = 0xxx dlm bits 7-0 = 0xxx rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs inverted spr bits 7-0 = 0xff i/o signals reset state tx logic 1 rts# logic 1 dtr# logic 1 rst logic 1 int three-state condition
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 22 test 1: the following inputs should remain steady at vcc or gnd state to minimize power down current: a0-a2, d0-d7, ior#, iow#, cs# and modem inputs. also, rx input must idle at logic 1 state while in power down mode. absolute maximum ratings power supply range 7 volts voltage at any pin gnd-0.3 v to 7 v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw typical package thermal resistance data ( margin of error : 15%) thermal resistance (48-tqfp) theta-ja = 59 o c/w, theta-jc = 16 o c/w thermal resistance (28-pdip) theta-ja = 57 o c/w, theta-jc = 23 o c/w thermal resistance (28-plcc) theta-ja = 55 o c/w, theta-jc = 28 o c/w electrical characteristics dc electrical characteristics u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97v to 5.5v s ymbol p arameter l imits 3.3v m in m ax l imits 5.0v m in m ax u nits c onditions v ilck clock input low level -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.4 vcc 3.0 vcc v v il input low voltage -0.3 0.8 -0.5 0.8 v v ih input high voltage 2.0 vcc 2.2 vcc v v ol output low voltage 0.4 v i ol = 6 ma v ol output low voltage 0.4 v i ol = 4 ma v oh output high voltage 2.4 v i oh = -6 ma v oh output high voltage 2.0 v i oh = -1 ma i il input low leakage current 10 10 ua i ih input high leakage current 10 10 ua c in input pin capacitance 5 5 pf i cc power supply current 1.3 3 ma i pwrdn power down current 50 200 ua see test 1
? ? ? ? st16c1450/51 rev. 4.2.0 2.97v to 5.5v uart 23 ac electrical characteristics ta = 0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97v to 5.5v s ymbol p arameter l imits 3.3v m in m ax l imits 5.0v m in m ax u nit c onditions clk clock pulse duration 63 21 ns osc oscillator/external clock frequency 8 24 mhz t as address setup time 5 0 ns t ah address hold time 10 5 ns t cs chip select width 50 40 ns t rd ior# strobe width 35 25 ns t dy read/write cycle delay 40 30 ns t rdv data access time 35 25 ns t dd data disable time 0 25 0 15 ns t wr iow# strobe width 40 25 ns t ds data setup time 20 15 ns t dh data hold time 5 5 ns t wdo delay from iow# to output 50 40 ns 100 pf load t mod delay to set interrupt from modem input 40 35 ns 100 pf load t rsi delay to reset interrupt from ior# 40 35 ns 100 pf load t ssi delay from stop to set interrupt 1 1 bclk t rri delay from ior# to reset interrupt 45 40 ns 100 pf load t si delay from stop to interrupt 45 40 ns t int delay from initial int reset to transmit start 8 24 8 24 bclk t rst reset pulse width 40 40 ns n baud rate divisor 1 2 16 -1 1 2 16 -1 - bclk baud clock 16x of data rate hz
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 24 f igure 8. c lock t iming f igure 9. m odem i nput /o utput t iming osc clk clk external clock iow# iow rts# dtr# cd# cts# dsr# int ior# ior ri# t wdo t mod t mod t rsi t mod active active change of state change of state active active active change of state change of state change of state active active
? ? ? ? st16c1450/51 rev. 4.2.0 2.97v to 5.5v uart 25 f igure 10. d ata b us r ead t iming f igure 11. d ata b us w rite t iming t as t dd t ah t rd t rdv t dy t dd t rdv t ah t as t cs valid address valid address valid data valid data a0- a2 cs2# ior# d0-d7 t cs t rd t as t dh t ah t wr t ds t dy t dh t ds t ah t as t cs valid address valid address valid data valid data a0- a2 cs2# iow# d0-d7 t cs t wr
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 26 f igure 12. r eceive r eady & i nterrupt t iming f igure 13. t ransmit r eady & i nterrupt t iming rx rxrdy (isr bit-5) ior# int d0:d7 start bit d0:d7 stop bit d0:d7 t ssr 1 byte in rhr active data ready active data ready active data ready 1 byte in rhr 1 byte in rhr t ssr t ssr rxnfm t rr t rr t rr t ssr t ssr t ssr (reading data out of rhr) tx txrdy (isr bit-4) iow# int* d0:d7 start bit d0:d7 stop bit d0:d7 t wt txnonfifo t wt t wt t srt t srt t srt *int is cleared when the isr is read and ier[1] is disabled. int cleared* int cleared* int cleared* (loading data into thr) (unloading) ier[1] enabled ier[1] enabled ier[1] enabled
? ? ? ? st16c1450/51 rev. 4.2.0 2.97v to 5.5v uart 27 package dimensions (48 pin tqfp - 7 x 7 x 1 mm ) note: the control dimension is the millimeter column inches millimeters symbol min max min max a 0.039 0.047 1.00 1.20 a 1 0.002 0.006 0.05 0.15 a 2 0.037 0.041 0.95 1.05 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.346 0.362 8.80 9.20 d 1 0.272 0.280 6.90 7.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 a 0 7 0 7 36 25 24 13 1 1 2 37 48 d d 1 d d 1 b e a a 2 a 1 a seating plane l c
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 28 package dimensions (28 pin pdip) note: the control dimension is the inch column inches millimeters symbol min max min max a 0.160 0.250 4.06 6.35 a 1 0.015 0.070 0.38 1.78 a 2 0.125 0.195 3.18 4.95 b 0.014 0.024 0.36 0.56 b1 0.030 0.070 0.76 1.78 c 0.008 0.014 0.20 0.38 d 1.380 1.565 35.05 39.75 e 0.600 0.625 15.24 15.88 e1 0.485 0.580 12.32 14.73 e 0.100 bsc 2.54 bsc ea 0.600 bsc 15.24 bsc eb 0.600 0.700 15.24 17.78 l 0.115 0.200 2.92 5.08 a 0 15 0 15
? ? ? ? st16c1450/51 rev. 4.2.0 2.97v to 5.5v uart 29 package dimensions (28 pin plcc) note: the control dimension is the inch column inches millimeters symbol min max min max a 0.165 0.180 4.19 4.57 a 1 0.090 0.120 2.29 3.05 a 2 0.020 - 0.51 - b 0.013 0.021 0.33 0.53 b1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.485 0.495 12.32 12.57 d 1 0.450 0.456 11.43 11.58 d2 0.390 0.430 9.91 10.92 d3 0.300 typ. 7.62 typ. e 0.050 bsc 1.27 bsc h1 0.042 0.056 1.07 1.42 h2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14
st16c1450/51 ? ? ? ? 2.97v to 5.5v uart rev. 4.2.0 30 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2003 exar corporation datasheet october 2003. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . revision history date revision descriptio n january 2003 rev 4.0.0 changed to single column format. clarified that the tx interrupt is not ms windows compatible. clarified timing diagrams. renamed rclk (receive clock) to bclk (baud clock) and timing symbols. added t ah , t cs and osc. april 2003 rev 4.0.1 updated ordering information. september 2003 rev 4.1.0 added status column to ordering information. october 2003 rev 4.2.0 clarified compatibility to industry standard 16450 and ms windows standard serial port driver in general description. removed auto rts flow control from mcr bit-1 description since that feature is not available in this device.
? ? ? ? st16c1450/51 2.97v to 5.5vuart rev. 4.2.0 i table of contents general description................................................................................................. 1 f eatures ............................................................................................................................... ...................... 1 a pplications ............................................................................................................................... ................ 1 f igure 1. b lock d iagram ............................................................................................................................... .............................. 1 f igure 2. st16c1450 p inouts ............................................................................................................................... ...................... 2 f igure 3. st16c1451 p inouts ............................................................................................................................... ...................... 3 ordering information ............................................................................................................................... .4 pin descriptions ......................................................................................................... 5 data bus interface ............................................................................................................. ................................ 5 modem or serial i/o interface .................................................................................................. ..................... 5 ancillary signals .............................................................................................................. .................................. 6 1.0 product description ..................................................................................................... ............... 7 2.0 functional descriptions ................................................................................................. ........... 7 2.1 internal registers ...................................................................................................... ............................. 7 2.2 crystal oscillator or external clock .................................................................................... ..... 8 2.3 programmable baud rate generator ........................................................................................ ..... 8 f igure 4. t ypical oscillator connections ............................................................................................................................... .. 8 2.4 transmitter ............................................................................................................. .................................... 9 2.4.1 transmit holding register (thr) - write only........................................................................... ................ 9 2.4.2 transmitter operation.................................................................................................. ..................................... 9 t able 1: t ypical data rates with a 14.7456 mh z crystal or external clock ........................................................................ 9 2.5 receiver ................................................................................................................ ...................................... 10 2.5.1 receive holding register (rhr) - read-only ............................................................................. ............... 10 f igure 5. t ransmitter o peration ............................................................................................................................... .............. 10 2.6 special (enhanced feature) mode ......................................................................................... .......... 11 2.6.1 soft reset ............................................................................................................. ................................................. 11 2.6.2 power down mode ........................................................................................................ ....................................... 11 2.7 internal loopback ...................................................................................................... .......................... 11 f igure 6. r eceiver o peration in non -fifo m ode .................................................................................................................... 11 f igure 7. i nternal l oopback ............................................................................................................................... ...................... 12 3.0 uart internal registers ................................................................................................. .......... 13 t able 2: st16c145x uart internal registers ......................................................................................... ...................... 13 t able 3: internal registers description. s haded bits are enabled when efr b it -4=1......................................... 14 4.0 internal register descriptions .......................................................................................... .. 15 4.1 receive holding register (rhr) - read- only ............................................................................. .. 15 4.2 transmit holding register (thr) - write-only ............................................................................ 15 4.3 interrupt enable register (ier) - read/write ............................................................................ . 15 4.4 interrupt status register (isr) - read-only ............................................................................. .. 15 4.4.1 interrupt generation: .................................................................................................. .................................... 16 4.4.2 interrupt clearing: .................................................................................................... ....................................... 16 4.5 line control register (lcr) - read/write ................................................................................ ..... 16 t able 4: i nterrupt s ource and p riority l evel ....................................................................................................................... 16 4.6 modem control register (mcr) or general purpose outputs control - read/write 18 t able 5: p arity selection ............................................................................................................................... ........................... 18 4.7 line status register (lsr) - read only .................................................................................. ......... 19 4.8 modem status register (msr) - read only ................................................................................. ... 20 4.9 scratch pad register (spr) - read/write ................................................................................. ..... 21 t able 6: uart reset conditions..................................................................................................... ................................... 21 absolute maximum ratings .................................................................................. 22 t ypical package thermal resistance data ( margin of error : 15%) ................................................. 22 electrical characteristics................................................................................ 22 dc e lectrical c haracteristics .............................................................................................................. 22 ac e lectrical c haracteristics .............................................................................................................. 23 ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97v to 5.5v...................... 23 f igure 8. c lock t iming ............................................................................................................................... ................................ 24 f igure 9. m odem i nput /o utput t iming ............................................................................................................................... ....... 24 f igure 10. d ata b us r ead t iming ............................................................................................................................... ............... 25 f igure 11. d ata b us w rite t iming ............................................................................................................................... ............. 25
st16c1450/51 ? ? ? ? rev. 4.2.0 2.97v to 5.5vuart ii f igure 12. r eceive r eady & i nterrupt t iming ......................................................................................................................... 26 f igure 13. t ransmit r eady & i nterrupt t iming ....................................................................................................................... 26 p ackage d imensions (48 pin tqfp - 7 x 7 x 1 mm ) ....................................................................................27 p ackage d imensions (28 pin pdip) ..........................................................................................................28 p ackage d imensions (28 pin plcc) .........................................................................................................29 r evision h istory ............................................................................................................................... ........30 t able of c ontents ............................................................................................................i

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